Batch wafer semiconductor process technologies have been heavily exploited not only to produce large scale integrated circuits, but a vast assortment of sensors and actuators as well. These include chemical sensors, photo detectors, radiation sensors, pressure transducers, temperature sensors, accelerometers, magnetic sensors, micro capillaries, micro mechanical devices, and many others. As semiconductor technologies advance and include increasing numbers of elements in a single “chip”, increasing numbers of layers of interconnect and their associated isolation dielectrics and passivation have become more common. In 150 nm generation technologies, 6-8 layers of copper, aluminum, or tungsten interconnect separated by low-capacitance dielectrics are not uncommon.
FIG. 1 is a cross-sectional view of such technology 100, showing a thick support silicon 102, a plurality of semiconductor devices (e.g. field-effect transistors) 104, an interconnect and dielectric stack 106, a protective passivation dielectric 108, and pads 110. The illustrated technology 100 of FIG. 1 is a simplified representation only and is intended to show relative placement. Additional or fewer features, layers, and or interconnects will likely be included in an actual device and/or wafer.
Complex semiconductor devices such as memory chips or microprocessors typically have many electrical connections (power, ground, input and output and bidirectional signals, extrinsic passive components, etc). With few exceptions, these electrical connections (signals) are brought to the “outside world” through a protective package, and connections between the semiconductor chip and the package are made through holes in the protective passivation to relatively large (2-6 mils) features on the top metal layer called “pads” (e.g. pads 110 in FIG. 1). At present there are two dominant methods for connecting the exposed top interconnect of these devices to the package. The first, illustrated in FIG. 2, is referred to as “wirebond” packaging. Wirebond packaging refers to attaching very thin conductive wires 202 between the metal pads 110 of the chip 100 and their appropriate conductive connections 204 in the package 206. In the case of wirebond the mechanical connection to the package is made from the bottom 208 of the semiconductor chip 100, while the electrical connections to the package are made from the top side 210 of the chip 100. The second, illustrated in FIG. 3, is referred to as “flip-chip” packaging. Flip-chip packaging refers to forming conducting bumps 302 on the exposed pads 110, flipping the chip 100 upside down, and placing those bumps 302 in direct connection with their associated conductive connections 304 in the package 306. Often an appropriate thermal process is used to partially melt the bumps 302 during the die attach step, so that the bumps 302 form good conductive and mechanical connection to their associated connections 304 in the package 306. A mechanical underfill or adhesive 308 may also be used to fill in the gaps between bumps 302. In the case of flip-chip packaging, mechanical and electrical connections to the package are made from the same side—the inverted top side 310 of the chip 100.
Wirebond has been the dominant approach to integrated circuit packaging until recently. Flip-chip is rapidly gaining acceptance for at least four reasons. 1) The relatively high inductance of bond wires introduces crosstalk, noise, and signal integrity issues. 2) Flip-chip affords more options for getting heat (generated as the semiconductor devices burn power) out of the package. 3) Wirebond necessitates that the electrical connections to the chip be organized in a ring around the chip's perimeter, while flip-chip affords the flexibility of making these electrical connections almost anywhere in the die, vastly increasing the number of possible electrical connections and the chip-design flexibility in where they may be placed. 4) Elimination of ball bonds, wires, and the package lid allows the overall thickness of the completed, packaged product to be reduced.
Regardless of whether flip-chip or wirebond is used, the presence of increasing numbers of layers of interconnect with increased pattern density is, in some cases, making it more difficult to use the underlying semiconductor elements in sensing applications. In addition, the ability in these fine-feature manufacturing technologies to incorporate additional films close to the underlying semiconductor devices suitable for sensing applications is limited by the complexity and sensitivity of the interconnect and isolation materials and structures.
Needed is a structure where the semiconductor devices are exposed for sensing applications, while the associated interconnect structures and their final connection to the package remain protected. Such a structure should be suitable for depositing additional films for the purpose of sensing without having to disturb the semiconductor, interconnect, passivation, or electrical package connection features.